The present invention relates generally to semiconductor devices and more particularly to methods for forming transistor source/drain regions having a sharp HDD portion buried within a graded HDD portion in the fabrication of semiconductor devices.
MOS transistors are found in many modern semiconductor products where switching and/or amplification functions are needed. Many manufacturing processes and techniques have been developed for fabricating MOS devices in semiconductor substrate materials such as silicon and the like. In recent years, the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products. At the same time, many new applications have created a need to operate transistors and other semiconductor devices at lower power and voltage levels. Thus, whereas previous MOSFET devices were designed to operate at voltages of 5 or more volts, newer applications may require such devices to operate from DC supplies of around 3 volts or less. In addition, switching speed requirements of MOS transistors continue to increase in order to facilitate faster and improved product performance. Accordingly, efforts continue to be made to design semiconductor devices, such as MOSFET transistors, which occupy less physical space, consume less power, and operate at higher switching speeds and at lower voltages.
MOS transistors include a conductive gate overlying a channel region of the substrate with a thin gate dielectric, typically oxide, therebetween. Source and drain regions of the substrate (sometimes referred to as junction regions) are doped with impurities on opposite sides of the channel, wherein the source/drain regions of NMOS devices are doped with n-type impurities (e.g., As, Sb, P, etc.) and PMOS devices are doped using p-type impurities (e.g., B, Ga, In, etc.). The length of the gate structure overlying the channel typically dictates the physical channel length thereunder. The source and drain dopants are typically implanted into the silicon substrate using ion implantation systems, wherein the dosage and energy of the implanted ions may be varied depending upon the desired dopant concentration, depth, and profile. The ion dosage generally controls the concentration of implanted ions for a given semiconductor material, and the energy level of the ions determines the distance of penetration or depth of the implanted ions (e.g., the junction depth).
One specific type of implant is the xe2x80x9cquad high-angle implantxe2x80x9d (QHA), which may be performed on the MOS device, wherein four separate high angle implants are done on the device wafer. Each implant is typically performed on the wafer held in a position, then rotationally indexed by 90 degrees.
Following implantation, the dopant atoms in the source/drain regions occupy interstitial positions in the substrate lattice, and the dopant atoms must be transferred to substitutional sites to become electrically active. This process is sometimes referred to as xe2x80x9cactivationxe2x80x9d, and is accomplished by high temperature annealing in an inert ambient such as argon. The activation anneal process also causes diffusion of implanted dopant species downward and laterally in the substrate, wherein the effective channel length becomes less than the gate width. As device sizes continue to shrink, the channel lengths continue to be scaled downward, wherein short channel effects become significant.
In addition to short channel effects, hot carrier effects are also experienced in short channel devices. For example, during saturation operation of a MOS transistor, electric fields are established near the lateral junction of the drain and channel regions. This field causes channel electrons to gain kinetic energy and become xe2x80x9chotxe2x80x9d. Some of these hot electrons traveling to the drain are injected into the thin gate dielectric proximate the drain junction. The injected hot carriers, in turn, often lead to undesired degradation of the MOS device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, and device instability.
To combat channel hot carrier effects, drain extension regions are commonly formed in the substrate, which are variously referred to as double diffused drains (DDD), lightly doped drains (LDD), and moderately doped drains (MDD). These drain extension regions absorb some of the potential into the drain and away from the drain/channel interface, thereby reducing channel hot carriers and the adverse performance degradation associated therewith.
The success of the MOS transistor has been partially due to the capability of the MOS transistor to take advantage of the lateral scaling improvements in the technologies. Lateral scaling results in simultaneous improvements in both the performance and the packing density of the devices. Although generalized scaling has served well for the last few decades, many of the technology advances that allow the devices to continue improving the performance and the packing density are approaching fundamental physical limitations.
Gate oxide thickness, junction scaling, and well engineering in MOS devices has enabled channel length scaling by improving short channel characteristics. By changing the doping profile in the channel region, the distribution of the electric field and potential contours can be changed. The goal is to optimize the channel profile to minimize the off-state leakage while maximizing the linear and saturation drive currents. Channel doping optimization can improve the circuit gate delay, for example, by about 10% for a given technology. Super Steep Retrograde Wells (SSRW) and halo implants (or pocket implants) have been used as a means to scale the channel length and increase the transistor drive current without causing an increase in the off-state leakage current.
The halo architecture creates a localized 2-D graded dopant distribution near the source/drain (S/D) regions and extends under the channel. Halos are generally known for their ability to stop unwanted source/drain leakage conduction, or punchthrough current, and as such, are sometimes referred to as xe2x80x9cpunchthrough stoppersxe2x80x9d.
Punchthrough current may also be seen as a parasitic current path existing between the drain and source, which is poorly controlled by the gate contact since the current path is located deeper in the bulk (substrate) farther from the gate. The actual amount of punchthrough current depends mainly on the potential distribution under the channel and on the S/D junction depths. As the effective channel length gets shorter, the S/D depletion regions also get closer. Punchthrough may then be established when the effective channel length is decreased to roughly the sum of the two junction depletion widths. One way to reduce the punchthrough current is to increase the overall bulk doping level. As a result, the drain and source depletion regions become smaller and may not establish a parasitic current path. Since a higher bulk doping increases the subthreshold swing, this method is not the most efficient way to reduce drain-source leakage.
Currently, super-sharp (SS) highly doped drain (HDD) profile junctions are commonly used to minimize channel resistance, extension region resistance, and source-drain resistance; (Rds) in a transistor. However, the SS HDD junction also increases the body-to-source/drain junction capacitance (Cqbw).
By contrast, graded HDD junction profiles have also been used to improve device performance; particularly with today""s deep sub-micron technologies, graded HDD profiles improve circuit performance with lower Cjbw or tunneling current. Graded HDD junctions may also advantageously lower the body-to-source/drain junction capacitance Cjbw, lower the band-to-band tunneling current, and reduce channel dopant segregation into the HDD (S/D) region. Graded HDD junctions may also permit better trimming (compensation) of the HDD profile with super-sharp retrograde SSR channels, reduce punchthrough current (subsurface DIBL), and lower the pocket dosage requirement. However, the graded HDD junction may have a higher source-drain resistance (Rds), because the graded region represents a high resistance region.
Segregation, in one instance, is the amount of channel dopant that diffuses into the HDD at the junction. That is, dopant segregation implies that there is a preferable region for migration of dopant atoms. For example, channel boron (xe2x88x92) dopants may tend to migrate across a junction toward an HDD arsenic (+) dopant concentration over time and temperature. However, with junctions that are more graded, there is less tendency for the boron dopants to migrate toward the HDD arsenic.
Thus attaining higher switching speeds in a MOS transistor, is seemingly at odds with either the super-sharp HDD or the graded HDD junction, as a higher drive current (Ids) is desirable, but at a lower body-to-source/drain junction capacitance Cjbw.
Several prior art methods have been used for forming transistor source/drain regions having a sharp HDD portion or a graded HDD portion in a semiconductor device. Before comparing these prior art methods, however, some relevant issues will be discussed in association with a conventional MOS transistor device of FIG. 1. FIG. 1 illustrates a conventional profile for the MOS transistor utilizing a drain extension or xe2x80x9ctailxe2x80x9d.
The MOS transistor 1 comprises a gate 2 having a channel length 2a, a gate-oxide 3, and a semiconductor substrate 4 with source/drain regions 5 on either side of a channel region 6. In the conventional MOS transistor 1, a deep source/drain junction 8 having a depth 8a is typically formed alongside a gate structure by implantation. The S/D region 5 has a drain extension or xe2x80x9ctailxe2x80x9d 10 which extends into and underlying the gate 2 and gate channel area 6. An enlarged detail 12 further illustrates the area surrounding the drain extension tail 10, and the manner in which the drain extension shortens the effective channel length by comparison to a transistor without this drain extension tail feature 10.
For example, FIG. 2, illustrates a profile for a conventional MOS transistor 20 similar to that of FIG. 1, but not utilizing a drain extension tail (e.g., 10 of FIG. 1), and as such may not be described in full detail again for the sake of brevity.
In FIG. 2, the MOS transistor 20 comprises a gate 22 having a channel length 22a, a gate-oxide 23, and a semiconductor substrate 24 with source/drain regions 25 on either side of a channel region 26. In the conventional MOS transistor 20, the S/D region 25 does not have a drain extension or xe2x80x9ctailxe2x80x9d, thus has a correspondingly longer channel length. Beneficially, a longer channel length minimizes the off-state leakage current by increasing the distance between the subsurface S/D regions, which reduces the subsurface leakage between the source and drain and other short channel effects.
Referring back to FIG. 1, in the fabrication process of the conventional MOS transistor 1, isolation structures (not shown) are formed in a substrate 4, and a gate oxide 3 (e.g., gate dielectric) is formed. A layer of polysilicon is deposited over the gate oxide 3, and is then patterned to form a polysilicon gate structure 2. Then, an LDD implant is performed, wherein drain extension regions are implanted using (e.g., As).
Since dopant impurities scatter mobility carriers and degrade linear drive current, ideally the dopant concentration near the substrate surface 4 and channel region 6 would be low. However, as previously discussed, drain extension regions or tails tend to require additional drain dopant compensation, which produces a higher bulk doping concentration in the channel region, and results in reduced carrier mobility. In addition, dopants from the drain extension of the conventional MOS transistor 1 may migrate further into the channel region further shortening the previously shortened channel length adding to the possible subsurface leakage current paths.
With a graded HDD, part of the dopant will also be implanted and migrate into the channel to form a tail in the channel region. If, for example, this dopant concentration in the tail is +1N, then an equal and opposite polarity dopant concentration of xe2x88x921N would be needed to compensate or trim the dopant profile in this tail. Further, to control or at least maintain the threshold voltage Vt of the MOS transistor, another xe2x88x921N dopant concentration may be added to this tail area of the channel region. However, since carrier mobility is actually affected by the gross or bulk doping concentration, the carrier mobility is affected by the gross dopant concentration of about 3N.
For example, a tail may receive an arsenic (+) dopant concentration of 1E18. To compensate for this dopant (dopant trimming), a boron (xe2x88x92) 1E18 dopant concentration may need to be added in the channel region. Then, to control or maintain the threshold voltage Vt of the MOS transistor, a second boron (xe2x88x92) 1E18 dopant concentration may need to be added. However, since the carrier mobility is actually affected by the gross or bulk doping concentration, the carrier mobility is affected by the gross dopant concentration of about 3E18. Thus, a super-sharp HDD is desirable to minimize the Rds, the scattering of carrier mobility, and the degradation of linear drive current when dopant impurities are added.
A second prior art method for forming transistor source/drain regions is the xe2x80x9cDual HDD processxe2x80x9d, which creates two steps in the profile according to FIG. 3.
FIGS. 3 illustrates a prior art method of forming a transistor source/drain region in a MOS transistor 30 according to the xe2x80x9cDual HDD processxe2x80x9d. The MOS transistor 30 comprises a gate structure 32 formed over a semiconductor substrate 34. Gate structure 32 comprises a gate-oxide material layer 36 formed over the semiconductor substrate 34, a polysilicon material layer 38 formed over the gate-oxide 36. This process is similar to other conventional processes, except that two HDD spacers and implant processes are used in the source/drain region 39.
In the xe2x80x9cDual HDD processxe2x80x9d, a first HDD spacer 40 comprising an insulative material is formed surrounding the gate 32, and a first HDD implant 42 is performed. Then, a second HDD spacer 44 comprising an insulative material is formed surrounding the first HDD spacer 40, and a second HDD implant 46 is performed. Then, a deep S/D spacer 48 comprising an insulative material is formed surrounding the second HDD spacer 44, and a deep S/D implant 49 is performed. This process relies on a final activation anneal after the deep S/D implant, which produces either a generally sharp profile across all junctions, or a generally graded profile across all junctions depending on the time and temperature used in the anneal process. It is desired, however, for a sharp profile only at the surface and graded elsewhere. The xe2x80x9cDual HDD processxe2x80x9d method is therefore generally unsuitable for the high device density and high-speed semiconductor applications contemplated.
A third prior art method for forming transistor source/drain regions is the xe2x80x9cDisposable spacer processxe2x80x9d, which seeks to produce the sharpest possible HDD profile. The xe2x80x9cDisposable spacer processxe2x80x9d method is based on the concept that the HDD region is the final implant process before the final activation anneal.
In this process, the sharp HDD profile at the surface benefits drive current, but also produces increased Cjbw (small depletion width), increased tunneling current (due to the sharp junction), a smaller spacing between HDD regions (less trimming by super-sharp retrograde channel doping), and interstitial dopant loss from the channel into HDD regions. Dopant is lost from the channel into the HDD regions because the sharper surface profile of this method produces a higher attraction electric field for the dopant. The xe2x80x9cDisposable spacer processxe2x80x9d method is therefore also generally unsuitable for the high device density and high-speed semiconductor applications contemplated.
A fourth prior art method for forming transistor source/drain regions is the xe2x80x9cHDD TIP processxe2x80x9d, which is similar to the second prior art method of the xe2x80x9cDual HDD processxe2x80x9d, except that the spacer step is skipped in place of a blanket implant step. As such, in the xe2x80x9cHDD TIP processxe2x80x9d, the blanket implant is performed without the first spacer process, saving the processing steps for the first HDD process. Since this method uses a blanket implant, it also saves the cost of two additional mask steps. However, it not only has all the disadvantages of the Dual HDD process, but also results in a slightly inferior PMOS or NMOS as the blanket TIP dopant and-the substrate dopant tend to counter dope each other. The xe2x80x9cHDD TIP processxe2x80x9d is therefore also generally unsuitable for the applications contemplated.
A fifth prior art method for forming transistor source/drain regions is the xe2x80x9cDual Dopant processxe2x80x9d. The xe2x80x9cDual Dopant processxe2x80x9d is typically used in older technology NMOS devices. Two species of different diffusivity are used in the HDD implant (e.g., arsenic and phosphorus). The high solid solubility and low diffusivity arsenic is used to produce the main conducting part of the HDD, whereas the high diffusivity phosphorus is used to produce a tail beyond the main conducting part of the HDD. This tail smoothes the HDD profile gradient and reduces hot carriers, tunneling current, and junction capacitance. Unfortunately, it will also degrade the drive current. The xe2x80x9cDual Dopant processxe2x80x9d is therefore also generally unsuitable for the applications contemplated.
In addition, as device densities and operational speeds continue to increase, reduction of the delay times in the MOS devices used in integrated circuits is desired. These delays are related to the on-state resistance as well as the junction capacitances of these MOS devices. In order to reduce these delays and increase MOS device speeds, improved source/drain regions as indicated are desired. Further, increasing device densities also result in a reduced source to drain distance, which requires that HDD dopant concentrations increase and move closer to the surface of the substrate. These changes may result in a disruption to the operation of a MOS transistor. In these and similar circumstances, certain aspects of the graded and the super-sharp HDD profile may help to avoid or mitigate some of the problems encountered, in the scaling of MOS devices.
What is needed to attain these higher switching speeds in a MOS transistor, is a higher drive current Ids, but at a lower body-to-source/drain junction capacitance Cjbw. Further, since the uppermost surface of the substrate (e.g., within 100 xc3x85), is responsible for controlling the bulk of the drive current, it is desirable to minimize the subsurface areas available for leakage and lower body-to-source/drain junction capacitance Cjbw.
Various aspects of graded and super-sharp HDD implants have been used as an additional means to scale MOS transistor channel length, increase drive current, decrease Rds, minimize off-state leakage current and the like of high-speed, high-density MOS devices. Several conventional approaches to form transistor source/drain regions have been discussed such as the xe2x80x9cDual HDD processxe2x80x9d approach, the xe2x80x9cDisposable spacer processxe2x80x9d, the xe2x80x9cHDD TIP processxe2x80x9d, the older xe2x80x9cDual Dopant processxe2x80x9d, and the conventional xe2x80x9cDeep S/D implantxe2x80x9d method. However, several difficulties encountered with each of these conventional approaches exist separately or in combination. Therefore, it is desirable to provide an improved method of forming a source/drain region to take advantage of several performance benefits of the graded and the super-sharp HDD profile in a MOS transistor, and in the manufacture of such semiconductor devices.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to methods for forming a transistor source/drain region having a sharp HDD portion buried within a graded HDD portion in the manufacture of semiconductor devices. The invention provides for the formation and activation annealing of a graded HDD region and source/drain regions. A sharp HDD region is formed over the graded HDD region, followed by a flash anneal. The 2-D dopant concentration profiles produced in the S/D regions and the channel-to-source/drain region junctions, according to the inventive method, yield several benefits of both the graded and sharp HDD profiles.
To implement the formation of a source/drain region having a sharp HDD portion buried within a graded HDD portion of a MOS transistor, several aspects of the present invention are provided. One aspect of the invention provides a method which comprises providing a gate structure overlying a semiconductor substrate, implanting a first dopant material alongside the gate structure to form a first graded HDD layer in a source/drain region of the semiconductor device. A sidewall spacer is formed around the gate structure to guide an implanting of a second dopant material to form the source/drain regions.
A first thermal anneal activates the dopant atoms in the source/drain region and establishes the graded HDD portion profile along with the source/drain region (which is also graded). An offset spacer and the sidewall spacer are removed from the gate structure, for example, by a wet or dry etch and an optional cleaning process to expose a substrate region closer to the gate structure for a final implanting and formation of a sharp or (e.g., a super-sharp) HDD region. A second thermal anneal (e.g., laser or flash anneal) establishes the sharp HDD portion-of the source/drain region having a sharp HDD profile at the substrate surface (e.g., within 100 xc3x85 of the surface), and overlying the graded HDD portion of the transistor S/D region.
Thus, a transistor source/drain region is formed, according to one aspect of the invention, having a sharp HDD portion buried within a graded HDD portion, wherein several characteristic benefits of each portion may be achieved. The goal is to provide sharp HDD regions close to the surface, and graded HDD regions elsewhere subsurface. In so doing, the sharp HDD portion of the S/D provides a low channel and HDD resistance, and a low source-drain resistance Rds.
In addition, the graded HDD portion of the S/D significantly improves junction capacitance and leads to improved circuit performance. For example, graded HDD junctions may advantageously lower the body-to-source/drain junction capacitance Cjbw, lower the band-to-band tunneling current, and reduce channel dopant segregation into the HDD (S/D) region because most of the HDD region profile is not sharp and the electric field potential is reduced. Graded HDD junctions may also permit better trimming (compensation) of the HDD profile with super-sharp retrograde SSR channels, reduce punchthrough current (subsurface DIBL), and lower the pocket dosage requirement because the gross HDD dopant concentration in the channel is lower.
In a further aspect of the invention, a quad high-angle implant (pocket dose) may be performed on the device around and underlying the edge of the gate structure before the first graded HDD implant process. In another aspect of the invention, the first thermal annealing may be a conventional activation thermal anneal (e.g., about 1050xc2x0 C. for about 1 second) used to activate the dopant atoms.
In another further aspect of the invention, an additional rapid thermal anneal (RTA) (e.g., about 950xc2x0 C. for about 1 second) may be used to remove excess interstitial dopant atoms after the graded HDD implant process.
Again, in a further aspect of the invention, the graded HDD region extends from the surface of the semiconductor substrate down to a depth of about 300 xc3x85, the source/drain region extends below the graded HDD region to a depth of about 1000 xc3x85, and the sharp HDD region extends from the surface of the semiconductor substrate down to a depth of less than about 100 xc3x85.
The improved formation method and dopant profiles achievable using the invention may be employed to provide formation of source/drain regions to take advantage of some of the potential performance benefits associated with both the sharp HDD portion and the graded HDD portion.